Software Drivers 29EE020 / 29LE020 / 29VE020 2 Megabit Page Mode EEPROM December 1997 ABOUT THE SOFTWARE This application note provides software driver examples for 29EE020, 2 Megabit Page Mode EEPROM, that can be used in any microprocessor based system. Software driver examples used in this document utilize two programming languages: (a) high -level "C" for broad platform support and (b) optimized 8086 assembly language. In many cases, software driver routines can be inserted "as is" into the main body of code being developed by the system software developers. Extensive comments are included in each rou- tine to describe the function of each routine. The driver in "C" language can be used with many microprocessors and microcontrollers, while the 8086 assembly language provides an optimized solution for 8086 microprocessors. NOTE: The 29EE020 is for 5.0 volt applications, the 29LE020 is for 3.0 volts application, and the 29VE020 is for 2.7 volt applications. Device functionality is identical for application of this software. For convenience, only the 29EE020 will be referenced in the example codes provided. ABOUT THE 29EE020 Companion product datasheets for the 29EE020 should be reviewed in conjunction with this application note for a complete understanding of the device. The recommended method for writing the 29EE020 employs the JEDEC approved "enable software pro- tection page write" (SDP) algorithm. Using this method, any write operation (128 bytes) requires the inclusion of a series of three byte-load operations, which precede the data loading operation. The three byte-load sequence enables the SDP option during page write operation. SDP provides optimal protection from inadvertent write cycles, e.g., those triggered by noise during the system power-up or power-down. After the initial data byte-load cycle, the host must continue to load a byte into the page buffer within the byte-load cycle time (TBLC) of 100 µs for the 29EE020 to stay in the page load cycle. Additional bytes can then be loaded within the same page, in any order. The page load cycle will terminate if no additional byte is loaded into the page buffer within 200 µs (TBLCO) from the last byte-load cycle, i.e. no subsequent WE# high-to-low transition after the last rising edge of WE#. Both the C and 8086 assembly code in the document contain the following routines, in this order: Name Function Check_SST_29EE020 Check manufacturer and device ID Write_29EE020 Alter data Check_Toggle_Ready End of write detection using Toggle bit Check_Data_Polling End of write detection using Data# polling Enable_Chip_Data_Protection Enable JEDEC standard software data protection "C" LANGUAGE DRIVERS /******************************************************************************************************/ /* Copyright Silicon Storage Technology, Inc. (SST), 1994-1997 */ /* Example "C" language Driver of 29EE020 2 Mbit Page Mode EEPROM */ /* Chi Chung Yin, Silicon Storage Technology */ /* */ /* Revision 2.0, April 8, 1997 */ /* */ /* This file requires these external "timing" routines: */ /* */ /* 1.) Delay_1_Milli_Second */ /* 2.) Delay_10_Milli_Second */ /* 3.) Delay_10_Micro_Second */ /******************************************************************************************************/ #define FALSE 0 #define TRUE (~FALSE) #define ROW_SIZE 128 /* Must be 128 bytes for 29EE020 */ #define SST_ID 0xBF /* SST Manufacturer’s ID code */ #define SST_29EE020 0x10 /* SST 29EE020 device code */ /* NOTE-Use "0x12" for 29LE020 and 29VE020 */ typedef unsigned char BYTE; /*____________________________________________________________________*/ /* EXERNAL ROUTINES */ /*____________________________________________________________________*/ extern void Delay_1_Milli_Second(); extern void Delay_10_Milli_Second(); extern void Delay_10_Micro_Second(); extern void Check_Toggle_Ready(BYTE far *); extern void Check_Data_Polling(BYTE far *, BYTE); ******************************************************************************************************/ /* PROCEDURE: Check_SST_29EE020 */ /* */ /* This procedure decides whether a physical hardware device has a SST */ /* 29EE020 2 Mbit Page Mode EEPROM installed or not. */ /* */ /* */ /* Input: */ /* None */ /* */ /* Output: */ /* return -1: indicates not a SST 29EE020 */ /* return 0: indicates is a SST 29EE020 */ /*****************************************************************************************************/ int Check_SST_29EE020() { BYTE far *Temp; BYTE SST_id1; BYTE SST_id2; int ReturnStatus; /* Issue the Software Product ID code to 29EE020 */ Temp = (BYTE far *)0xC0005555; /* set up address to be C000:5555h */ *Temp = 0xAA; /* write data 0xAA to the address */ Temp = (BYTE far *)0xC0002AAA; /* set up address to be C000:2AAAh */ *Temp = 0x55; /* write data 0x55 to the address */ Temp = (BYTE far *)0xC0005555; /* set up address to be C000:5555h */ *Temp = 0x90; /* write data 0x90 to the address */ Delay_10_Milli_Second(); /* Read the product ID from 29EE020 */ Temp = (BYTE far *)0xC0000000; /* set up address to be C000:0000h */ SST_id1 = *Temp; /* get first ID byte */ Temp = (BYTE far *)0xC0000001; /* set up address to be C000:0001h */ if ((SST_id1 == SST_ID) && (SST_id2 ==SST_29EE020)) ReturnStatus = 0; else ReturnStatus = -1; / /* Issue the Soffware Product ID Exit code thus returning the 29EE020 */ /* to the read operating mode */ Temp = (BYTE far *)0xC0005555; /* set up address to be C000:5555h */ *Temp = 0xAA; /* write data 0xAA to the address */ Temp = (BYTE far *)0xC0002AAA; /* set up address to be C000:2AAAh */ *Temp = 0x55; /* write data 0x55 to the address */ Temp = (BYTE far *)0xC0005555; /* set up address to be C000:5555h */ *Temp =0xF0; /* write data 0xF0 to the address */ Delay_10_Milli_Second(); return(ReturnStatus); } /******************************************************************************************************/ /* PROCEDURE: Write_29EE020 */ /* */ /* This procedure can be used to write a total of 128 bytes at one write cycle to the */ /* SST’s 29EE020. */ /* */ /* Input: */ /* SRC SOURCE address containing the data which will be */ /* written into the 29EE020. */ /* Dst DESTINATION address which will be written with the */ /* data passed in from ds:si */ /* */ /* Output: */ /* None */ /******************************************************************************************************/ void Write_29EE020 (BYTE far *Src, BYTE far *Dst) { BYTE far *Temp; BYTE far *SourceBuf; BYTE far *DestBuf; int Index; SourceBuf = Src; DestBuf = Dst; /************************************************************************************/ /* WRITTEN OPERATION */ /* */ /* Issue the 3-byte "enable protection" sequence followed by 128 bytes */ /* of data written to the 29EE020. */ /************************************************************************************/ Temp = (BYTE far *)0xC0005555; /* set up address to be C000:555h */ *Temp = 0xAA; /* write data 0xAA to the address */ Temp = (BYTE far *)0xC0002AAA; /* set up address to be C000:2AAAh */ *Temp = 0x55; /* write data 0x55 to the address */ Temp = (BYTE far *)0xC0005555; /* set up address to be C000:5555h */ *Temp = 0xA0; /* write data 0xA0 to the address */ for (Index = 0; Index < ROW_SIZE; Index++) { *DestBuf++ = *SourceBuf++; /* transfer data from source to destination */ } Delay_1_Milli_Second(); /* wait 1ms to start writing */ Check_Toggle_Ready(Dst); /* wait for TOGGLE bit to get ready */ } /******************************************************************************************************/ /* PROCEDURE: Check_Toggle_Ready */ /* */ /* During the internal write cycle, any consecutive read operation */ /* on DQ6 will produce alternating 0’s and 1’s i.e. toggling between */ /* 0 and 1. When the write cycle is completed, DQ6 of the data will */ /* stop toggling. After the DQ6 data bit stops toggling, the device is ready */ /* for next operation. */ /* */ /* Input: */ /* Dst must already set-up by the caller */ /* */ /* Output: */ /* None */ /******************************************************************************************************/ void Check_Toggle_Ready (BYTE far *Dst) { BYTE Loop = TRUE; BYTE PreData; BYTE CurrData; unsigned long TimeOut = 0; PreData = *Dst; PreData = PreData & 0x40; while ((TimeOut< 0x07FFFFFF) && (Loop)) { CurrData = *Dst; CurrData = CurrData & 0x40; if (PreData == CurrData) Loop = FALSE; /* ready to exit the while loop */ PreData = CurrData; TimeOut++; } } /******************************************************************************************************/ /* PROCEDURE: Check_Data_Polling */ /* */ /* During the internal write cycle, any attempt to read DQ7 of the last byte loaded during */ /* the page/byte-load cycle will receive the complement of the true data. Once the */ /* write cycle is completed, DQ7 will show true data. */ /* */ /* Input: */ /* Dst must already set-up by the caller */ /* True Datathis is the original (true) data */ /* */ /* Output: */ /* None */ /******************************************************************************************************/ void Check_Data_Polling (BYTE far *Dst, BYTE TrueData) { BYTE Loop = TRUE; BYTE CurrData; unsigned long TimeOut = 0; TrueData = TrueData & 0x80; while ((TimeOut< 0x07FFFFFF) && (Loop)) { CurrData = *Dst; CurrData = CurrData & 0x80; if (TrueData == CurrData) Loop = FALSE; /* ready to exit the while loop */ TimeOut++; } } /******************************************************************************************************/ /* PROCEDURE: Enable_Chip_Data_Protection */ /* */ /* This procedure ENABLES the data protection feature on the 29EE020 */ /* 2 Mbit Page Mode EEPROM. After calling this routine, the chip cannot be written */ /* unless preceded by the three Byte-Load sequence. */ /* */ /* Input: */ /* None */ /* */ /* Output: */ /* None */ /******************************************************************************************************/ void Enable_Chip_Data_Protection() { BYTE far *Temp; Temp = (BYTE far *)0xC0005555; /* set up address to be C000:5555h */ *Temp = 0xAA; /* write data 0xAA to the address */ Temp = (BYTE far *)0xC0002AAA; /* set up address to be C000:2AAAh */ *Temp = 0x55; /* write data 0x55 to the address */ Temp = (BYTE far *)0xC0005555; /* set up address to be C000:5555h */ *Temp = 0xA0; /* write data 0xA0 to the address */ Delay_10_Milli_Second(); } 8086 ASSEMBLY LANGUAGE DRIVERS ; ==================================================================== ; Copyright Silicon Storage Technology, Inc. (SST), 1994-1997 ; EXAMPLE 8086 assembly Drivers for 29EE020 2 Mbit Page Mode EEPROM ; Chi Chung Yin, Silicon Storage Technology ; ; Revision 2.0, April 8, 1997 ; ; This file requires these external "timing" routines: ; ; 1.) Delay_1_Milli_Second ; 2.) Delay_10_Milli_ Second ; 3.) Delay_10_Micro_Second ; ==================================================================== ROW_SIZE EQU 128 ;Must be 128 bytes for 29EE020 SST_ID EQU 0BFh ;SST Manufacturer’s ID code SST_29EE020 EQU 010h ;SST 29EE020 internal code ;NOTE-Use "012h" for 29LE020 and 29VE020 ABS_SEGMENT EQU 0C000h extrn Delay_1_Milli_Second:near extrn Delay_10_Milli_Second:near extrn Delay_10_Micro_Second:near ;======================================================================= ; PROCEDURE: Check_SST_29EE020 ; ; This procedure decides whether a physical hardware device has a SST’s ; 29EE020 2 Mbit Page Mode EEPROM installed or not. ; ; Input: ; None ; ; Output: ; carry bit: SET means not a SST 29EE020 ; carry bit: CLEARED means a SST 29EE020 ; ;======================================================================= Check_SST_29EE020 proc near push ax ; preserve registers’ value push ds cli mov ax, ABS_SEGMENT mov ds, ax mov ds:byte ptr [5555h], 0AAh ; issue the 3-byte product ID mov ds:byte ptr [2AAAh], 055h ; command to the 29EE020 mov ds:byte ptr [5555h], 090h call Delay_10_Micro_Second ; wait until Tww expires mov al, ds:[0] cmp al, SST_ID ; is this a SST part? jne CSC5 ; NO, then return Carry set mov al,ds:[1] cmp al, SST_29EE020 ; Is it 29EE020? jne CSC5 ; NO, then Non-SST part CSC4: clc pushf ; save the result on the STACK jmp short CSC6 CSC5: stc ; save the result on the STACK pushf CSC6: ; ; Issue the Software Product ID Exit code thus returning the 29EE020 ; to the read operation mode. ; mov ds:byte ptr [5555h], 0AAh ; issue the 3-byte product ID mov ds:byte ptr [2AAAh], 055h ; exit command to the 29EE020 mov ds:byte ptr [5555h], 0F0h call Delay_10_Micro_Second ; wait until Tww expires popf ; restore result from the stack pop ds ; restore original values pop ax ret Check_SST_29EE020 endp ; ===================================================================== ; PROCEDURE: Write_29EE020 ; ; This procedure can be used to write a total of 128 bytes at one write cycle to the ; SST’s 29EE020. ; ; Input: ; ds:si SOURCE address containing the data which will be ; written into the 29EE020. ; es:di DESTINATION address which will be written with the ; data passed in for ds:si ; ; Output: ; None ; SI, DI: Contains the original values ; ===================================================================== Write_29EE020 proc near push ax push bx push cx push di push si pushf ; preserve the "Direction" flag in the FLAG ; register cld ; clear "Direction" flag in the FLAG register ; auto-increment SI, and DI ; ===================================================================== ; WRITE OPERATION ; Let’s issue the 3-byte "Enable Protection" sequence to the 29EE020 ; chip followed by the 128 bytes of data. ; ===================================================================== push ax push ds mov ax, ABS_SEGMENT mov ds, ax mov ds:byte ptr [5555h], 0AAh ; 3 bytes of "enable protection" mov ds:byte ptr [2AAAh], 055h ; sequence to the chip mov ds:byte ptr [5555h], 0A0h pop ds pop ax mov cx, ROW_SIZE ; we will write 128 bytes push si ; save original values push di cli ; no disturb allowed while in the process ; of writing the 29EE020. DRP1: lodsb ; do not use "rep movsb" instruction stosb ; loop DRP1 ; write 128 bytes call Delay_1_Milli_Second ; wait 1ms to start writing pop di ; restore original values pop si call check_Toggle_Ready ; wait for TOGGLE bit to get ready popf pop si pop di pop cx pop bx pop ax ret Write_29EE020 endp ;====================================================================== ; PROCEDURE: Check_Toggle_Ready ; ; During the internal write cycle, any consecutive read operation ; on DQ6 will produce alternating 0’s and 1’s, i.e. toggling between ; 0 and 1. When the write cycle is completed, the DQ6 data will ; stop toggling. After the DQ6 data stops toggling, the device is ready ; for the next operation. ; ; Input: ; es:di must already set-up by the calller ; ; Output: ; None ;====================================================================== Check_Toggle_Ready proc near push ax mov al, es:[di] ; read a byte form the chip and al,40h ; mask out the TOGGLE bit (DQ6) CTR_Tog2: mov ah, es:[di] ; read the same byte from the chip again and ah, 40h ; mask out the TOGGLE bit (DQ6) cmp al, ah ; is DQ6 still toggling? je CTR_Tog3 ; No, then the write operation is done xchg ah, al ; YES, then continue checking... jmp short CTR_Tog2 CTR_Tog3: pop ax ret Check_Toggle_Ready endp ;======================================================================= ; PROCEDURE: Check_Data_Polling ; ; During the internal write cycle, any attemp to read DQ7 of the last byte loaded during ; the page/byte-load cycle will receive the complement of the true data. Once the ; write cycle is completed, DQ7 will show true data. ; ; Input: ; es:di must already set-up by the caller ; bl contains the original (true) data ; ; Output: ; None ; ;======================================================================= Check_Data_Polling proc near push ax and bl, 80h ; mask out the DQ7 bit CDP_Tog2: mov al, es:[di] ; read a byte from the chip and al,80h ; mask out the DQ7 bit cmp al,bl ; is DQ7 still complementing? jne CDP_Tog2 pop ax ret Check_Data_Polling endp ;======================================================================= ; PROCEDURE: Enable_Chip_Data_Protection ; ; This procedure ENABLES the data protection feature on the 29EE020 ; 2 Mbit Page Mode EEPROM. After calling the routine, the chip cannot be written ; unless preceded by the three Byte-Load sequence. ; ; Input: ; None ; ; Output: ; None ;======================================================================= Enable_Chip_Data_Protection proc near push ax ; preserve registers’ value push ds cli mov ax, ABS_SEGMENT mov ds, ax mov ds:byte ptr [5555h], 0AAh ; issue the 3-byte protect mov ds:byte ptr [2AAAh], 055h ; sequence to the 29EE020 mov ds:byte ptr [5555h], 0A0h call Delay_10_Milli_Second pop ds pop ax ret Enable_Chip_Data_Protection endp