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SuperFlash Cell Technology
Three Generations of Split-Gate Non-Volatile Memory
SuperFlash® memory cell was originally invented by Bing Yeh, SST's founder. The memory cell has evolved beyond the first generation, enhancing the scaling of the cell from 1µm technology node to 65nm and smaller geometry. Through scaling and evolution, the memory cell retains its split-gate structure, poly-to-poly Fowler-Nordheim (FN) tunneling erase, and Source-Side Hot Channel Electron (SS HCE) injection programming.
The first generation SuperFlash® cell has been used in both stand-alone and embedded flash memory products for over 15 years. This non-self-aligned double-poly cell has floating-gate poly as a storage element and 3 nodes for read, erase, and program operations: select-gate (WL), source (SL), and drain (BL). The floating-gate and select-gate channels are split between source and drain.
The beauty of the first generation SuperFlash® lies in the simplicity of forming the memory cell in a given logic process. The field enhanced tunneling injector on the floating poly is formed using standard CMOS oxidation and dry etching processes. The WL poly is inherently the logic poly. Drain and source are created with logic junction formation. The first generation cell has been scaled from 1µm to 0.13µm technology node and beyond.
To enhance scaling, SuperFlash® cell was innovated with the second generation self-aligned memory technology. While flash macro with up to 8Mb memory density is ideal for the first generation SuperFlash® technology, the smaller cell of the second generation allows system designers to incorporate macro with memory array density higher than 8Mb.
The advancement of the ESF2 cell comes with self-aligning processing steps in forming the floating-gate, source line poly, and WL poly, thus reducing the number of mask required to create the memory cell. The floating-gate element is self-aligned to the formation of active. The source line poly and WL poly are self-aligned to floating-gate poly and dielectric spacers.
To further enhance the scaling of the split-gate memory cell, the coupling gate (CG) is introduced in SuperFlash®'s third generation technology. In addition, erase gate (EG), formed with select-gate (WL) poly as well as logic gate poly, is separated from the select-gate. This separation of the erase gate from the select transistor allows the scaling of the select transistor. The gate oxide under WL in the 3rd generation cell has the flexibility of adopting either the core logic gate oxide or the IO transistor gate oxide. With the assistance of the coupling gate, the source junction can be scaled back thus providing further improvement on the scaling of the floating-gate channel. In short, the aggressive scaling of the third generation cell enables designing flash macro with very high memory array density.
SuperFlash® technology has enabled designers to create cost effective and high performance programmable SOC solutions through the use of SST's proprietary split-gate flash memory cell. With the scaling from 1µm technology node to 65nm technology node over the past 20-year history of the company, the memory cell maintains its split-gate structure, fundamental operation conditions, a simple array architecture thus simplifying design, low power and high performance, silicon CMOS compatibility with good scalability, and excellent reliability.
Split-Gate Structure:
In general, the split-gate cell consists of a floating gate, a select-gate which may also function as an erase-gate, a source, and a drain. This is a one-and-a-half transistors cell and its size is comparable to that of the traditional stacked-gate cell for a given technology node. The channel, split between the drain and source, is a series combination of the floating-gate and select-gate transistors. The select-gate portion of the channel isolates the floating gate-portion from the drain which prevents over-erase, a common issue found in stacked-gate memory cells. The split-gate memory is programmed using source side channel hot electron (SS CHE) injection and erased using poly-poly Fowler-Nordheim (FN) tunneling between floating and select-gates.