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- SuperFlash
- SuperFlash Cell
- Three SuperFlash Generations
- ESF1 SuperFlash Cell
ESF1 SuperFlash Cell
The first generation SuperFlash® cell has been used in both stand-alone and embedded flash memory products for over 15 years. This non-self-aligned double-poly cell has floating-gate poly as a storage element and 3 nodes for read, erase, and program operations: select-gate (WL), source (SL), and drain (BL). The floating-gate and select-gate channels are split between source and drain.
The beauty of the first generation SuperFlash® lies in the simplicity of forming the memory cell in a given logic process. The field enhanced tunneling injector on the floating poly is formed using standard CMOS oxidation and dry etching processes. The WL poly is inherently the logic poly. Drain and source are created with logic junction formation. The first generation cell has been scaled from 1mm to 0.13mm technology node and beyond.
General Process Flow:
The memory array is arranged in cross-point architecture with rows of word-lines and columns of bit lines. The rows can be segmented into big blocks or small sectors, suitable for a wide range of embedded flash applications. During erase operation, a voltage is applied to the word-lines that erase all the cells in one pulse. The poly-to-poly tunneling with the field enhanced injector facilitates fast erase time (~1ms). Cells can be programmed in bits or page with relatively low voltage on SL. To create channel hot electrons at the gap region between the select-gate and the floating-gate channels during program, the select transistor is slightly turned on with a small voltage on the select-gate and a small programming current applied to the bit line. The memory cell is read with Vcc on the word-line and a reference voltage on the bit line.
