SST > SuperFlash > SuperFlash Cell > Three SuperFlash Generations

ESF3 SuperFlash Cell

To further enhance the scaling of the split-gate memory cell, the coupling gate (CG) is introduced in SuperFlash®'s third generation technology. In addition, erase gate (EG), formed with select-gate (WL) poly as well as logic gate poly, is separated from the select-gate. This separation of the erase gate from the select transistor allows the scaling of the select transistor. The gate oxide under WL in the 3rd generation cell has the flexibility of adopting either the core logic gate oxide or the IO transistor gate oxide. With the assistance of the coupling gate, the source junction can be scaled back thus providing further improvement on the scaling of the floating-gate channel. In short, the aggressive scaling of the third generation cell enables designing flash macro with very high memory array density.

The process of forming the third generation cell is simpler than that of the second generation cell, despite of the additional nodes to enhance the scaling and performance. The floating-gate is self-aligned to active and coupling gate. Both word-line and erase gate come from logic poly-silicon deposition. Drain and source junctions come from standard logic process.

The addition of the coupling gate and separation of the erase gate allow the competitive scaling of the SuperFlash cell to 65nm technology node and finer geometries.

The memory cell operation is fundamentally unchanged from previous two SuperFlash® generations. Cell is programmed using the highly efficient SS CHE injection mechanism. With additional coupling from the coupling gate, source voltage used for programming is significantly reduced, thus alleviating programming disturb. Flexibility in coupling gate decoding also helps to expand the program-programming disturb window. Fast erase is done with poly-to-poly tunneling using the erase gate which helps to maintain the high endurance and SILC immunity characteristics.

With word-line decoupled from high voltage erase, the select transistor can be optimized for high cell current with core logic supply voltage. This is ideal for low voltage, low power, and high performance applications.