(SST) CMOS SuperFlash EEPROM technology and the SST field enhancing tunneling injector split-gate memory cell. The SuperFlash^®  technology and memory cell have a number of important advantages for designing and manufacturing flash EEPROMs, or embedding SuperFlash memory in logic devices, when compared with the thin oxide stacked gate or two transistor approaches. These advantages translate into significant cost and reliability benefits for the user. The SST SuperFlash^®  technology typically uses a simpler process with fewer masking layers, compared to other flash EEPROM approaches. The fewer masking steps significantly reduces the cost of manufacturing a wafer. Reliability is improved by reducing the latent defect density, i.e., fewer layers are exposed to possible defect causing mechanisms. The SST split-gate memory cell is comparable in size to the single transistor stacked gate cell (for a given level of technology), yet provides the performance and reliability benefits of the traditional two transistor byte alterable E2PROM cell. By design, the SST split-gate memory cell eliminates the stacked gate issue of "overerase", by isolating each memory cell from the bit line. "Erase disturb" cannot occur because all bytes are simultaneously erased in the same page and each page is completely isolated from every other page during any high voltage operation.