Papers and Publications
The following papers have been published by or in conjunction with SST engineers, related to SuperFlash® technology.
- S. Kianian, A. Levi, D. Lee, and Y.-W. Hu, "A novel 3 Volts only, small sector erase, high density flash EEPROM," in VLSI Symp. Tech. Dig.,1994, pp. 71‒72.
- R. Mih, J. Harrington, K. Houlihan, H. K. Lee, K. Chan, J. Johnson, B. Chen, J. Yan, A. Schmidt, C. Gruensfelder, K. Kim, D. Shum, C. Lo, D. Lee, A. Levi, and C. Lam, "0.18 µm modular triple self-aligned embedded split-gate memory," in VLSI Symp. Tech. Dig., 2000, pp. 120‒121.
- Kotov, A. Levi, Y. Tkachev, and V. Markov, "Tunneling phenomenon in SuperFlash cell", Proc. NVM Tech. Symp., 2002, pp. 110‒115.
- H. Guan, D. Lee, and G.P. Li, "An analytical model for optimization of programming efficiency and uniformity of split gate source-side injection SuperFlash memory", IEEE Trans. El. Dev., V.50, No.3, 2003, pp.809‒815.
- V. Markov, X. Liu, A. Kotov, A. Levi, T. N. Dang, and Y.Tkachev, “SuperFlash® Memory Program/Erase Endurance", Proc. NVM Tech. Symp., 2003, pp. 231‒234.
- Y. Tkachev, X. Liu, A. Kotov, V. Markov, and A. Levi, “Observations of single electron trapping/detrapping events in tunnel oxide of SuperFlash® memory cell," in Proc. NVM Tech. Symp., 2004, pp. 45‒50.
- X. Liu, V. Markov, A. Kotov, T. N. Dang, A. Levi, I. Yue, A. Wang, and R. Qian, "Endurance characteristics of SuperFlash® memory", Proc. ICSICT, 2006, pp.763‒765.
- Y. Tkachev and A. Kotov, "Detection of single-electron transfer events and capacitance measurements in submicron floating-gate memory cells," in Proc. ESSDERC, 2006, pp. 411‒414.
- V. Markov, K. Korablev, A. Kotov, X. Liu, Y. B .Jia, T. N. Dang, and A. Levi, "Charge-gain program disturb mechanism in split-gate flash memory cell", IIRW Final Report, pp.43‒47, 2007.
- Y. Tkachev and A. Kotov, "Generation of single-and double-charge electron traps in tunnel oxide of flash memory cells under Fowler-Nordheim stress", IIRW Final Report, pp.101‒104, 2011.
- Y. Tkachev, X. Liu, and A. Kotov, "Floating-gate corner-enhanced poly-to-poly tunneling in split-gate Flash memory cells", IEEE Trans. El. Dev., V.59, No.1, 2012, pp.5‒11.