First Generation - ESF1

SuperFlash® technology is based on a proprietary split-gate flash memory cell which provides a cost effective and high performance programmable SoC solution. The SuperFlash split-gate memory cell reliably maintains its fundamental structures and operation conditions within its simple array architecture delivering a robust solution since 1997.

SuperFlash® is characterized by possessing the following capabilities:

  • Simplified Design
  • Low power and high performance standard silicon CMOS compatibility
  • Good scalability from 1µm technology node to 110nm technology node
  • High endurance to rewrite cycling
  • Excellent data retention with extremely low failure rate
  • Good performance at high temperature
  • Immunity to stress-induced leakage current (SILC)

The fundamental principle of SuperFlash technology involves the reading of the bit cell by applying reference voltages to the selected gate via the word line and also to the drain via the bit line while the source is grounded. Reference voltage applied on the word line turns ‘ON’ the select gate portion of the channel; the cell then conducts current if the floating gate is erased (in its low threshold state).

However, the cell is non-conductive if the floating gate is programmed (in its high threshold state). The conductive cell outputs logic "1" and the non-conductive cell outputs logic "0". The cell read through the control of the select transistor eliminates the "over erase" issue encountered in typical stacked-gate flash memory cells.

The SuperFlash split-gate flash memory cell is comparable in size to the single-transistor stacked-gate cell (for a given level of technology/process node), yet it provides the performance and reliability benefits of the traditional two-transistor byte-alterable EEPROM cell. SuperFlash technology uses poly-to-poly Fowler-Nordheim tunneling for erasing and source-side channel hot electron injection for programming. Poly-to-poly tunneling is from a field enhancing tunneling injector formed on the floating-gate using industry standard oxidation and dry etching techniques. Source-side channel hot electron injection is very efficient, thus allowing the use of a small on-chip charge pump from a single low-voltage power supply, e.g. 5 or 3 volts. Cells are normally erased prior to programming.

In general, the split-gate cell consists of:

  • Floating gate
  • Select-gate, doubles as an erase-gate,
  • Source

The simplicity of the cell structure eliminates many of the peripheral logic functions needed to control erasing of the stacked gate device. The channel, split between the drain and source, is a series combination of the floating-gate and select-gate transistors. The select-gate portion of the channel isolates the floating gate-portion from the drain which prevents over-erase, a common issue found in stacked-gate memory cells. "Erase disturb" cannot occur because all Bytes are simultaneously erased in the same page and each page is completely isolated from every other page during any high-voltage operation. The tunneling injector cell can be formed using standard CMOS process. Memory arrays may use either random access or sequential access peripheral architectures.

There are 2 types of programming disturbs known to the split-gate memory cell that can easily be mitigated by proper design and optimized process:

  • Punch-Through And Reverse Tunneling Programming Disturbs – This effect is suppressed by inhibiting the unselected bit lines with Vcc (row punch-through) or by inhibiting the unselected word-lines with 0V (column punch-through).
  • Reverse Tunneling Disturb – This effect may occur on the unselected erased cell; with inhibit bit line that shares the same source line of the cell being programmed. This occurs when electrons are transferred from word-line poly to floating-gate poly. This disturb can be prevented with process optimization.