Summary

Floating gate reprogrammable EEPROMs, whether called flash memories, EPROMs, or byte alterable E²PROMs, can be compared on performance, cost, reliability, and technology. Performance, cost, and reliability are directly related to the design and wafer process technology. This paper will compare the three major approaches to producing these various EEPROMs: the thin oxide stacked gate approach; the thin oxide two transistor cell; and the thick oxide split-gate cell patented by SST. These are all random access approaches, e.g., NOR. A variation of the two transistor cell is used by some manufacturers for sequential access approaches, e.g., NAND. The SST cell may also be used for sequential access architectures. This paper will review the basic technology for each approach and show the impact on performance, cost, and reliability.